With greater integration, the power dissipation in integrated circuits has begun to outpace the ability of today’s heat sinks to limit the on-chip temperature. As a result, thermal issues have come to the forefront, and thermally aware design techniques are likely to play a major role in the future. The scope of this design contest is to motivate participants in order to propose new design tools and/or design techniques that alleviate the on-chip thermal stress, without affecting the performance metrics of the target system.
The challenges that should be addressed within this design contest are summarized at the complementary priorities:
Challenge No. 1: Physical design for ICs under Thermal and Performance metrics: Participants should propose a software-supported methodology that addresses the floorplanning problem for 2-D ICs. The proposed solutions will be implemented as part (or as a new) software tool.
Challenge No. 2: Detailed thermal analysis: Given the floorplans for each benchmark (as they are retrieved from HotFloorplanning tool at Challenge No. 1) participants are encouraged to develop a new thermal simulator (or enhance an existing one) in order to support fast yet accurate thermal analysis.
Both challenges aim to optimize the following metrics:
Benchmark suite is provided here that contains all the necessary information for performing both floorplaning and thermal analysis. More specifically, each design in the benchmark suite will contain the following information:
The submitted floorplans and thermal analysis will be evaluated by the following metrics:
The reference solutions for the scoring criteria 1-3 will be derived with Hotfloorplan and Hotspot v.6 tools (see http://lava.cs.virginia.edu/HotSpot/) from University of Virginia. For this purpose, default settings will be employed, whereas details about the grid size will be released along with benchmarks. Regarding the total wirelength (criterion 4), Manhattan distance between pair of architectural components will be considered multiplied by the number of wires that connect these components (if there is no connection, the corresponding weight for this pair of components is equals to 0).
Details of the metrics and scoring system will be released on this page.
Please make note of the following dates:
Registration fees for the participation in the design contest: 300 Euros
A full or student registration includes one participation in the design contest (additional fees for the design contest, in case you have paid for author registration, are not needed). Registration fees are paid though the registration platform of PATMOS (in Registration tab). For the contestants who participates only to the design contest the corresponding registration fees should be paid until 24 July 2017.
There will be prizes awards to the top three teams. The first team will be awarded with a tablet.
Submission deadline (Regular Papers):
May 8, 2017 May 29, 2017
Submission deadline (Special Sessions):
May 15, 2017 May 29, 2017
Notification of acceptance:
June 26, 2017 July 3, 2017
Camera-ready papers due:
July 24, 2017