on Monday, 25 September 2017
Plenty of Room at the Bottom? Micropower
Deep Learning for IoT end-nodes
Abstract: Deep Neural Networks are being regarded today as an extremely effective and flexible approach for extracting actionable, high-level information from the wealth of raw data produced by a wide variety of sensory data sources. DNNs are however computationally demanding: today they typically run on GPU-accelerated compute servers or high-end embedded platforms. Industry and academia are racing to bring DNN inference (first) and training (next) within ever tighter power envelopes, targeting mobile and wearable applications. Recent results, including our PULP and ORIGAMI chips, demonstrate there is plenty of room at the bottom: pj/OP (GOPS/mW) computational efficiency, needed for deploying DNNs in the mobile/wearable scenario, is within reach. However, this is not enough: 1000x energy efficiency improvement, within a mW power envelope and with low-cost CMOS processes, is required for deploying DNNs in IoT end-nodes and implantable systems. The sub-mW, fj/OP milestone will require heterogeneous (3D) integration with ultra-efficient die-to-die communication, mixed-signal pre-processing, event-based approximate computing.
Short CV: Luca Benini holds the chair of digital Circuits and systems at ETHZ and he is a Professor at the Universita di Bologna. Dr. Benini's research interests are in energy-efficient system design for embedded and high-performance computing. He is also active in the area of energy-efficient smart sensors and ultra-low power VLSI design. He has published more than 800 papers, five books and several book chapters. He is a Fellow of the IEEE and the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award.
on Tuesday, 26 September 2017
Robust architectures for yield, lifespan, reliability, low-power,
and performance enhancements
Abstract: As CMOS technologies are approaching their ultimate limits, fabrication yield, reliability, lifespan, and power densities, worsen steadily and make further nanometric scaling increasingly difficult. These problems would become showstoppers in pushing aggressively ultimate-CMOS and post-CMOS scaling, unless efficient fault-mitigation and low-power approaches are developed to maintain acceptable levels of yield, reliability, and power densities. Furthermore, even before blocking technology scaling, these issues are also making increasingly difficult meeting the low power and high performance requirements, which are paramount in numerous applications. Resolving these issues is facing several well-known stringent constraints: supply voltage reduction, often used to reduce power, affects yield, reliability, and lifespan, by reducing noise margins that increase the sensitivity to soft-errors and EMI, and by increasing circuit delays and thus the severity of timing faults; extra circuitry used in fault mitigation architectures increase power. Furthermore, reducing supply voltage for reducing power affects performance by increasing circuit delays; increasing clock frequency for increasing performance, affects drastically power as it increases dynamic power, and may also require increasing supply voltage for reducing circuit delays. To address these issues, this talk describes recent advances in robust architectures, which enable drastic improvements of yield, reliability, lifespan, power dissipation, and performance in both, logic designs and memories, including: a framework of robust architectures, which mitigate timing issues in logic designs by enabling tolerance of up to 100% delay increases; and a framework of robust architectures for memories, which enables tolerating huge levels of defect densities, for which, conventional fault mitigation hardware, like built-in self-repair, consumes up to 1600% power with respect to the memory under repair, while for the new framework of robust memory architectures this dissipation is less that 7.5% and can be exploited by means of a reuse approach, for achieving high yield, reliability, and lifespan, low power, and high performance, in future Ultimate CMOS and post-CMOS technologies that are expected to be affected by very high fault rates.
Short CV: Michael Nicolaidis is research Director at the French National Research Council (CNRS) and member of the TIMA Laboratory where he leads the RIS group. His research interests include among others Design for Test, Design for Yield, Design for Reliability, and Design for Low Power. He authored 31 patents. He has more that 240 cited publications and more than 6000 citations. He authored one book and edited two books and several journal special issues. He received four Best Paper Awards (3 at DATE & 1 at IEEE VTS). One of his papers was selected among the most important papers of the 25 first years of the IEEE Fault-Tolerant Computing Symposium (FTCS), and another one among the most influential papers of the 10 years of DATE. He is Golden Core Member of the IEEE Computer Society. He was plenary keynote speaker in several international conferences. He also was: member of the editorial board of the IEEE Design & Test of Computers, Steering Committee member of VTS, IOLTS, and IRVW, and he was also member of the Steering Committee of ITC from 2012 to 2015. He is the Past-Chair of the Test Technology Technical Council (TTTC) of the IEEE Computer Society, and was the elected Chair of TTTC from 2012 to 2015. He is founder of iRoC Technologies. Michael Nicolaidis also introduced several new concepts that gained extensive use in the industry and academia, including among others: the parallel memory-BIST architecture, which was quickly adopted by the industry for replacing the preexisting serial BIST and the random BIST architectures; the transparent memory test and BIST, which allows testing memories in the context of application execution without modifying their contents, and is adopted by numerous industrial sectors including automotive electronics, and is also integrated in the tools of major EDA vendors; the complex-coupling and concurrent-coupling fault models for multiport memories, and the related families algorithms, which are adopted by the whole electronics industry in replacement of the single-port memory fault models and test algorithms that were used till then for testing multi-port memories; as well as the double-sampling architecture, which reduce drastically the cost of error detection, in comparison with conventional error detection architectures, and attracted wide interest after is use in the Razor architecture and the related processor implementations. Last but not least, some other of his innovations were licensed to major EDA vendors.
on Wednesday, 27 September 2017
Nonlinear Dynamics of Circuits with CMOS Memristor Emulators
Abstract: Tremendous efforts are spent to the realization of memristors and to memory technology. The development of memristor based neuron models and synapses play an important role in several recent investigations. Therefore, appropriate device models have to be derived and usually numerically solved in circuit simulations. On the other side, CMOS memristor emulators represent a suitable tool to develop, to test, and to analyze new types of circuits showing a complex behavior in highly efficient information processing systems.
This contribution will give a theoretical approach to circuits with first-order CMOS memristors. Results will be discussed based on a circuit inspired by Chua’s circuit showing the emergence of chaotic behavior.
Short CV: Ronald Tetzlaff is a Full Professor of Fundamentals of Electrical Engineering at the Technische Universitδt Dresden, Germany. His scientific interests include problems in the theory of signals and systems, stochastic processes, physical fluctuation phenomena, system modelling, system identification, Volterra systems, Cellular Nonlinear Networks, and Memristive Systems. From 1999 to 2003 Ronald Tetzlaff was Associate Editor of the IEEE, Transactions on Circuits and Systems: part I. He was "Distinguished Lecturer" of the IEEE CAS Society (2001-2002). He is a member of the scientific committee of different international conferences. He was the chair of the 7th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2002) and organized several special sessions at circuit and systems related conferences. From 2005 to 2007 he was the chair of the IEEE Technical Committee Cellular Neural Networks & Array Computing. Ronald Tetzlaff is a member of the Informationstechnische Gesellschaft (ITG) and the German Society of Electrical Engineers and of the German URSI Committee. Ronald Tetzlaff is in the Editorial Board of the International Journal of Circuit Theory and Applications since 2007 and he is also in the Editorial Board of the IEEE, Transactions on Circuits and Systems: part II since 2016. He was Associate Editor of the AEά – International Journal of Electronics and Communications from 2008 to 2016. Ronald Tetzlaff was the chair of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2010), the chair of the 5th International Workshop on Seizure Prediction (IWSP5 2012) , the chair of the 21st European Conference on Circuit Theory and Design (ECCTD 2013), the chair of the 5th Memristor and Memristive Symposium 2016, and of the 15th IEEE International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2016). Since 2014 her serves as the leader of working group 2 (Memristor Theory, Modelling and Simulation) in the EU COST action MemoCIS (IC 1401) on Memristors - Devices, Models, Circuits, Systems and Applications. Ronald Tetzlaff serves as a reviewer for several journals and for the European Commission.
Submission deadline (Regular Papers):
May 8, 2017 May 29, 2017
Submission deadline (Special Sessions):
May 15, 2017 May 29, 2017
Notification of acceptance:
June 26, 2017 July 3, 2017
Camera-ready papers due:
July 24, 2017