on Monday, 25 September 2017
Plenty of Room at the Bottom? Micropower
Deep Learning for IoT end-nodes
Abstract: Deep Neural Networks are being regarded today as an extremely effective and flexible approach for extracting actionable, high-level information from the wealth of raw data produced by a wide variety of sensory data sources. DNNs are however computationally demanding: today they typically run on GPU-accelerated compute servers or high-end embedded platforms. Industry and academia are racing to bring DNN inference (first) and training (next) within ever tighter power envelopes, targeting mobile and wearable applications. Recent results, including our PULP and ORIGAMI chips, demonstrate there is plenty of room at the bottom: pj/OP (GOPS/mW) computational efficiency, needed for deploying DNNs in the mobile/wearable scenario, is within reach. However, this is not enough: 1000x energy efficiency improvement, within a mW power envelope and with low-cost CMOS processes, is required for deploying DNNs in IoT end-nodes and implantable systems. The sub-mW, fj/OP milestone will require heterogeneous (3D) integration with ultra-efficient die-to-die communication, mixed-signal pre-processing, event-based approximate computing.
Short CV: Luca Benini holds the chair of digital Circuits and systems at ETHZ and he is a Professor at the Universita di Bologna. Dr. Benini's research interests are in energy-efficient system design for embedded and high-performance computing. He is also active in the area of energy-efficient smart sensors and ultra-low power VLSI design. He has published more than 800 papers, five books and several book chapters. He is a Fellow of the IEEE and the ACM and a member of the Academia Europaea. He is the recipient of the 2016 IEEE CAS Mac Van Valkenburg award.
on Tuesday, 26 September 2017
Fast and Accurate CPS Simulation for the masses
Abstract: One of the main problems the CPS designers face is “the lack of simulation tools and models for system design and analysis”. This is mainly because the majority of the existing simulation tools for complex CPS handle efficiently only parts of a system (e.g. only the processing nodes or only the network) while they mainly focus on the performance. Moreover, they require extreme amounts of processing resources and computation time to accurately simulate the CPS nodes’ processing. Faster approaches are available, however as they function at high levels of abstraction, they cannot provide the accuracy required to model the exact behavior of the system under design so as to guarantee that it meets the requirements in terms of performance and/or energy consumption. So there is an imminent need for a simulator which will seamlessly simulate, in an integrated way, both the networking and the processing parts of the CPS, orders of magnitude faster than the existing systems while providing much more accurate results, especially in terms of power consumption, than existing solutions. In this talk we will present such an approach which is based on a processing simulation sub-system (i.e. a “full-system simulator”), integrated in a novel manner with a state-of-the-art network simulator and a modern power estimator. The presented innovative simulator is orders of magnitude faster, while also being more accurate and reporting more CPS aspects, than existing systems, by applying hardware acceleration through the use of field programmable gate arrays (FPGAs).
Short CV: Prof. Ioannis Papaefstathiou is an Associate Professor at the School of Electronic and Computer Engineering at the Technical University of Crete, Greece. He has also been an Associate Professor at Rochester Institute of Technology (RIT) in Computer Security from 2014 to 2015. Previously, he has been a researcher at Foundation of Research and Technology Hellas (FORTH), a visiting assistant professor at the University of Crete and the University of Thessaly and a Manager at Ellemedia Technologies Ltd. He was granted a PhD degree in computer science at the University of Cambridge UK, in 2001, an M.Sc. degree from Harvard University, Cambridge, MA, USA in 1997 and a B.Sc. degree from the University of Crete, Greece in 1996. He is working in the design and implementation methodologies for HPC and embedded systems with tightly coupled design parameters and highly constrained resources. He has published more than 100 papers in IEEE-sponsored journals and conferences. He has been the guest editor of a special issue of IEEE Micro and he got the Best-Paper award at IEEE ESTIMEDIA 2012. He has been the Principal Investigator in 15 competitively funded research projects in Europe (in 7 of them he was the technical manager), in the last 8 years, where, in those projects, the cumulative budget share of the organizations he has been working at exceeds €5 million.
on Wednesday, 27 September 2017
Nonlinear Dynamics of Memristor Circuits in Locally Coupled Network
1Institute of Circuits and Systems, TU Dresden, Germany
2Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy
3Department of Electrical Engineering and Computer Sciences, University of California
Berkeley, Berkeley, CA 94720 USA
Abstract: Tremendous efforts are spent to the realization of memristors and to memory technology. The development of memristor based neuron models and synapses play an important role in several recent investigations. Therefore, appropriate device models have to be derived and usually numerically solved in circuit simulations. Especially, appropriate models of fabricated memristors are considered, to test, and to analyze new types of array computing technology showing a complex behavior in highly efficient information processing systems.
This contribution will give a theoretical approach to circuits with higher-order memristors. First results will be discussed based on an array of locally coupled identical memristor circuits showing a huge potential for future information processing systems.
Short CV: Ronald Tetzlaff is a Full Professor of Fundamentals of Electrical Engineering at the Technische Universitδt Dresden, Germany. His scientific interests include problems in the theory of signals and systems, stochastic processes, physical fluctuation phenomena, system modelling, system identification, Volterra systems, Cellular Nonlinear Networks, and Memristive Systems. From 1999 to 2003 Ronald Tetzlaff was Associate Editor of the IEEE, Transactions on Circuits and Systems: part I. He was "Distinguished Lecturer" of the IEEE CAS Society (2001-2002). He is a member of the scientific committee of different international conferences. He was the chair of the 7th IEEE International Workshop on Cellular Neural Networks and their Applications (CNNA 2002) and organized several special sessions at circuit and systems related conferences. From 2005 to 2007 he was the chair of the IEEE Technical Committee Cellular Neural Networks & Array Computing. Ronald Tetzlaff is a member of the Informationstechnische Gesellschaft (ITG) and the German Society of Electrical Engineers and of the German URSI Committee. Ronald Tetzlaff is in the Editorial Board of the International Journal of Circuit Theory and Applications since 2007 and he is also in the Editorial Board of the IEEE, Transactions on Circuits and Systems: part II since 2016. He was Associate Editor of the AEά – International Journal of Electronics and Communications from 2008 to 2016. Ronald Tetzlaff was the chair of the 18th IEEE Workshop on Nonlinear Dynamics of Electronic Systems (NDES 2010), the chair of the 5th International Workshop on Seizure Prediction (IWSP5 2012) , the chair of the 21st European Conference on Circuit Theory and Design (ECCTD 2013), the chair of the 5th Memristor and Memristive Symposium 2016, and of the 15th IEEE International Workshop on Cellular Nanoscale Networks and their Applications (CNNA 2016). Since 2014 her serves as the leader of working group 2 (Memristor Theory, Modelling and Simulation) in the EU COST action MemoCIS (IC 1401) on Memristors - Devices, Models, Circuits, Systems and Applications. Ronald Tetzlaff serves as a reviewer for several journals and for the European Commission.
Submission deadline (Regular Papers):
May 8, 2017 May 29, 2017
Submission deadline (Special Sessions):
May 15, 2017 May 29, 2017
Notification of acceptance:
June 26, 2017 July 3, 2017
Camera-ready papers due:
July 24, 2017